1. Field of the Invention
The present invention relates to a semiconductor memory device including a plurality of memory cell regions, and more particularly, to improvement of a read/write gate of a semiconductor memory device and a high speed access operation.
2. Description of the Background Art
The semiconductor memory device industry is moving rapidly towards a larger storage capacity and a higher operation speed. This trend is particularly significant in the field of a DRAM (Dynamic Random Access Memory) where a memory cell is formed of one capacitor and one MOS transistor in a compact structure.
FIG. 8 shows a structure of such a semiconductor memory device. Referring to FIG. 8, a semiconductor memory device includes a sense amplifier region 1, a plurality of memory cell regions 2 arranged in a matrix of rows and columns, four row decoders 3, four column decoders 4, a word line coupling region 5 provided parallel to the memory cell regions in the row direction, an empty region 6, a read/write circuit 7, and a control circuit 66.
The plurality of memory cell regions 2 are symmetrized about the dot dash line in FIG. 8. The memory cell regions 2 at the left and right sides of the dot dash line are further symmetrized about the sense amplifier region 1.
The sense amplifier region 1 is located between a pair of memory cell regions 2 provided in the column direction. This sense amplifier region 1 is provided with a sense amplifier, an input/output gate and the like as will be described afterwards.
The control circuit 66 generates various signals for controlling the semiconductor memory device according to a row address strobe signal /RAS, a column address strobe signal /CAS, a write signal /WE, and an address signal Add. The generated signals include a block selecting signal .phi. indicated by a hollow arrow in the figure, an internal address signal (merely referred to as an "address signal" hereinafter) applied to the row decoder 3 and the column decoder 4, and an internal read/write signal for controlling the read/write circuit 7.
The row decoder 3 selects a word line WL in response to an address signal to pull the selected word line WL to a H level (logical high). The sense amplifier provided in the sense amplifier region 1 amplifies the data of a memory cell connected to the selected word line WL. The column decoder 4 selects a desired bit from the memory cells of one row of the selected word line WL in response to an address signal.
The word line coupling region 5 serves to reduce the impedance of a word line WL.
FIG. 9 shows a structure of the word line WL indicated by the broken line in FIG. 8. Because the word line WL has a high resistance due to the fact that it is generally formed of a polysilicon layer, the time constant takes a high value when the word line rises. The resistance of a word line is reduced by short-circuiting the aluminum interconnection and the polysilicon interconnection in the word line coupling region 5 provided parallel to the memory cell regions 2 in the column direction. As a result, the time constant at the time of the rise of the word line is reduced to allow a higher speed of operation of the semiconductor memory device.
As an alternative of connecting the aluminum interconnection and the polysilicon interconnection, a buffer circuit formed of two stages of inverters may be provided in the word line coupling region 5, as shown in FIG. 10. This gives the advantage of preventing delay in the word line selecting signal. The word line coupling method and the method of providing a buffer circuit both have the impedance of the word line reduced.
FIG. 11 schematically shows a layout of the portion surrounded by the chain line with one dot in FIG. 8. Referring to FIG. 11, the portion surrounded by a chain line with one dot B includes a word line 40, bit lines BL and /BL, and a contact hole 41. Contact holes 41 are arranged in upper and lower stages so as not to form a contact with each other. The polysilicon layer and the aluminum interconnection are overlayed as shown in FIG. 9 to be connected by the contact hole 41 in the word line coupling region 5.
The empty region 6 is a region surrounded by the word line coupling regions 5 and the sense amplifier regions 1, establishing a margin in the layout. Although two MOS transistors 42 and 43 are provided in this region 6 as will be described afterwards with reference to FIG. 12, it is considered substantially as an empty region.
FIG. 12 is a circuit diagram showing the portion surrounded by a chain line with two dots A in FIG. 8 showing a structure of a conventional semiconductor memory device. Referring to FIG. 12, the sense amplifier region 1 to the left of the dot dash line includes NMOSFETs 7, 8, 11 and 12 serving as memory cell region selecting gates, NMOSFETs 9 and 10 serving as input/output gates, a circuit 39 including a sense amplifier and a bit line equalize circuit, and a sub-I/O line pair of SIO1 and /SIO1. The sense amplifier region 1 located at the right hand side of the dot dash line is similar to the sense amplifier region 1 located at the left hand side of the dot dash line, and includes NMOSFETs 25, 26, 29, and 30 serving as memory cell region selecting gates, NMOS transistors 27 and 28 serving as input/output gates, a circuit 39 including a sense amplifier and an equalize circuit, and a sub-I/O line pair of SIO3 and /SIO3.
The empty region 6 located at the left hand side of the dot dash line includes NMOSFETs 42 and 43 serving as block selecting gates. The empty region 6 located at the right hand side of the dot dash line includes NMOSFETs 44 and 45 serving as block selecting gates. The signal .phi.1 in FIG. 12 is a signal for selecting the block to the left of the dot dash line when attaining a high level. The signal .phi.2 is a signal for selecting the block to the right of the dot dash line. The signal .phi.S1 selects the memory cell regions located at the left-hand side of the sense amplifier region 1 in the region to the left of the dot dash line. The signal .phi.S4 selects the memory cell regions located at the right-hand side of the sense amplifier region 1 in the region to the left of the dot dash line. Similarly, signals .phi.S3 and .phi.S4 are signals for selecting the memory cell regions at the left-hand side and the right-hand side, respectively, of the sense amplifier region 1 in the region to the right of the dot dash line.
Signal BLEQ serves to equalize the potential of the bit line pair.
The circuit 39 equalizes the potential of the bit lines BL and /BL and detects the potential difference of bit lines BL and /BL. The details of this circuit 39 are shown in FIG. 13. Referring to FIG. 13, the circuit 39 includes a sense amplifier 39S responsive to sense amplifier driving signals .phi.P and .phi.N for detect-amplifying the potential difference of bit lines BL and /BL, and an equalize circuit 39E responsive to a bit line equalize signal BLEQ for equalizing the potential of bit lines BL and /BL to a half of the power supply potential Vcc. Sense amplifier driving signals .phi.P and .phi.N are complementary to each other.
FIG. 14 is a timing chart of the semiconductor memory device of FIG. 12.
The reading and writing operation of the data of memory cell 21 in FIG. 12 will be described with reference to the timing chart of FIG. 14.
At time t1, a row address signal is latched when the row address strobe signal /RAS attains a L level (logical low). At time t2, the signal .phi.S1 for selecting a memory cell region attains a L level and the word line WL1 connected to the access gate of the memory cell 21 attains a H level according to the row address signal. The signal .phi.S2 for selecting the memory cell regions of the righthand side maintains a H level. In response to signal .phi.S2, the memory cell region selecting gates 7 and 8 are turned off and the memory cell region selecting gates 11 and 12 are turned on. Thus, the data of the memory cell 21 is read out to the bit line BL2, whereby a potential difference is generated between the bit line pair BL2 and /BL2.
At time t3, when the sense amplifier 39S is activated, the potential difference of the bit line pair BL2 and /BL2 is amplified. At time t4, the column decoder 4 pulls the column selecting signal Yi to a H level according to a column address signal. The block selecting signal .phi.1 attains a H level and the block selecting gates 42 and 43 are turned on. As a result, the bit line pair BL2 and /BL2, the sub-I/O line pair SIO2 and /SIO2, and the main I/O line pair GIO2 and /GIO2 are connected, whereby the potentials of the bit line pair BL2 and /BL2 are transmitted to the main I/O line pair GIO2 and /GIO2. The read/write circuit 7 shown in FIG. 8 detects the potential difference of the main I/O line pair GIO2 and /GIO2 to identify the data maintained in the memory cell 21. The data held in the memory cell 21 is logical high when the potential of the main I/O line GIO2 is higher than that of /GIO2, and is logical low when the potential of the main I/O line GIO2 is lower than that of /GIO2.
At time t5 when the write signal /WE attains a L level, the write data applied to the main I/O lines GIO2 and /GIO2 is supplied to bit lines BL2 and /BL2 via the sub-I/O lines SIO2 and /SIO2, whereby data is written into the memory cell 21.
Because the structure of FIG. 12 has the sub-I/O line pair and the main I/O line pair connected to the bit line pair when the column selecting signal Yi attains a H level, the column selecting signal Yi must be pulled up to the H level after the potential difference is amplified by the sense amplifier 39S.
This is because the sub-I/O lines and main I/O lines having a great parasitic capacitance will be connected to the bit line when the column selecting signal Yi is brought to a H level prior to a sense amplifying operation to result in a small potential difference between the bit lines BL2 and /BL2, leading to a possibility of erroneous operation caused by the sense amplifier failing to amplify the small potential difference.
There is a conventional circuit shown in FIG. 15 for solving such a problem. FIG. 15 is a circuit diagram showing an example of structure of a conventional semiconductor memory device. The semiconductor memory device of FIG. 15 differs from the semiconductor memory device of FIG. 12 in that NMOSFETs 46-49 serving as read out gates in the sense amplifier region located at the left side of the dot dash line, and NMOSFETs 52 and 53 for selecting a read out block in the empty region 6 located below the sense amplifier region 1 are added. Similarly, NMOSFETs 56-59 serving as read out gates in the sense amplifier region 1 located at the right-hand side of the dot dash line and NMOSFETs 62 and 63 for selecting a read out block in the empty region 6 provided beneath the sense amplifier region 1 are added. A sub-output line pair of SO1 and /SO1 exclusively for reading and a sub-input line pair of SI1 and /SI1 exclusively for writing are provided.
FIG. 16 is a timing chart for showing the operation of the semiconductor memory device of FIG. 15.
The operation of reading out data from the memory cell 21 of FIG. 15 and writing an inverted data will be described with reference to the timing chart of FIG. 16.
At time t1 where the row address strobe signal /RAS attains a L level, a row address signal is latched. The row decoder 3 pulls the word line WL1 to a H level according to the row address signal. In response, the address gate of the memory cell 21 is turned on, whereby the data in memory cell 21 is read out to the bit line pair BL and /BL. At time t3, the column selecting signal YRi is brought to a H level to conduct NMOSFETs 48 and 49, and the block selecting signal .phi.1 is brought to a H level to conduct NMOSFETs 52 and 53. Because the potential of bit line BL2 is higher than that of the bit line /BL2, NMOSFET 46 is turned on more heavily than NMOSFET 47. Therefore, the potentials of the sub-output line SO1 and the main I/O line GIO2 become lower than the respective potentials of the sub output line /SO1 and the main I/O line GIO2. The read/write circuit 7 detects the potential difference between main I/O lines GIO and /GIO to identify the data held in the memory cell 21. When the potential of the main I/O line GIO is lower than that of /GIO, the memory cell data is logical high. When the potential of the main I/O line GIO is higher than that of /GIO, the memory cell data is logical low.
As described above, the semiconductor memory device of FIG. 15 differs from the semiconductor memory device of FIG. 12 in that the column selecting signal YRi is brought to a H level before the sense amplifying operation and reads out the memory cell data to main I/O line pair GIO2 and /GIO2. This offers an advantage of a faster read out operation of the memory cell data to the main I/O line pair of GIO2 and /GIO2.
At time t4 when the write signal /WE is brought to a L level, the column selecting signal YWi attains a H level, whereby the data in the main I/O line is applied to the bit line. Then, the potential of the bit line BL2 is written to the memory cell 21.
The conventional semiconductor memory device of the above-described structure has the width W2 of the sense amplifier region 1 in the column direction of FIG. 15 increased in comparison with the width W1 of the sense amplifier region in the column direction of FIG. 12 for increasing the read out speed of data when the structure of FIG. 12 is implemented as shown in FIG. 15. This results in a problem of increase in the chip area.